Using Proteus and Cyclone ii for the practical teaching of VHDL and FPGA through software and hardware
DOI:
https://doi.org/10.31381/perfilesingenieria.v21i22.7299Keywords:
FPGA, cyclone II, VDL, PROTEUSAbstract
This article aims to work with PROTEUS and the Cyclone II FPGA to design a 3-bit counter circuit in software and hardware. For the software part, PROTEUS will be used, and it comes with the GAL22v10, a reprogrammable CPLD manufactured by the company Lattice Semiconductors. The VHDL description will be made using the Cypress Warp Galaxy software, it generates a .jed file from the constructed VHDL file, the .jed file is used to record it in the GAL and thus be able to simulate the description made. The Galaxy software is free to use and a virtual machine is required because it works with Windows XP. Virtual Box will be used as Virtualization software belonging to the ORACLE company. Regarding the FPGA, the cyclone II ep2ct144c8n from the INTEL FPGA company will be used. Which will be programmed with the Quartus II 13.0 sp1 software. As a result, the circuit will be simulated in PROTEUS with the GAL 22V10 and in hardware with the cyclone II card.
Downloads
References
INTEL, “Cyclone II Device Handbook, Volume 1”, 2008. [En línea]. Available: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc2/cyc2_cii5v1.pdf.
INTEL, “Descargar software QUARTUS II”, 2021. [En línea]. Available: https://www.intel.com/content/www/us/en/software-kit/666221/intel-quartus-ii-web-edition-design-software-version-13-1-for-windows.html
INTEL-ALTERA, “Quartus II Handbook Version 13.1. Volume 1: Design and Synthesis”, 2013. [En línea]. Available: https://www.intel.com/content/www/us/en/softwarekit/666221/intelquartusiiwebedition-design-software-version-13-1-for-windows.html
A. Ivanova, “A Concept of Visual Programming Tool for Learning VHDL”, IOP Conference Series: Materials Science and Engineering, 2020.
E. Saeed, Basics VHDL Labs. Basics Lab for Learning VHDL. Learning with Experiments, Al Nahrain. Irak: Lap Lambert, 2020.
L. Chuquimarca, P. Suárez y F. López, “Simulación electrónica del microprocesador GAL22V10 mediante el software Proteus basado en VHDL para virtualizar circuitos integrados”, Revista Científica y Tecnológica UPSE, vol. 8, nº 1, pp. 107 - 115, 2021.
P. Kumar, “Development of Programmable Logic Devices”, International Journal of Innovative Research in Computerand Communication Engineering, vol. 8, nº 4, 2020.
R. Chopra, “A Review Paper on Virtualization”, International Journal of Innovative Research in Computer Science & Technology (IJIRCST), vol. 10, nº 2, pp. 131-135, 2022.
B. Sundstrom, Virtualization [undergraduate thesis]. University of Virginia, Charlottesville, Virginia, 2023.
P. Valencia, D. Garcia, S. Mena y J. Erazo, “Virtualbox como estrategia de enseñanza aprendizaje en la asignatura de soporte técnico”, Cienciamatria, vol. 6, nº 3, 2020.
M. Muhammad, I. Ismahani, S. Shahidatul y M. Musa, “The effectiveness of complex programmable logic device for learning digital systems during the COVID-19 pandemic”, Symposium on Teaching & Learning Practices in Electrical Engineering. Malaysia, 2021.
S. Syahminan y C. Hidayat, “Development of digital engineering learning with proteus software media and emulators department of informatics engineering Kanjuruhan University”, Annual Conference on Science and Technology (ANCOSET 2020), vol. 1869, 2020.
F. Chengcheng, L. Xiang, L. Ronghua y S. Boyu, “Application of proteus in Experimental Teaching and Research of Medical Electronic Circuit”, Advances in Social Science, Education and Humanities Research, vol. 215, 2018.
INTEL, “Intel FPGA USB Download Cable User Guide”, 2016. [En línea]. Available: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr.pdf.
S. Naing, N. San y T. Chao, “FPGA Based Digital Logic Circuits Operation for Beginners”, International Journal of Trend in Scientific Research and Development (IJTSRD), vol. 3, nº 5, pp. 495-501, 2019.
R. Deepack, “Design and Analysis of Digital Counters for VLSI Applications”, International Research Journal of Engineering and Technology (IRJET), vol. 3, nº 7, 2016.
H. Cao y U. Meyer, “XML-Based Automatic NIOS II Multi-Processor System Generation for Intel FPGAs”, Electronics, 2022.
T. Goethals, M. Sebrechts, M. Al-Naday, B. Volckaert y F. De Turck, “A Functional and Performance Benchmark of Lightweight Virtualization Platforms for Edge Computing”, IEEE International Conference on Edge Computing and Communications (EDGE), pp. 60-68, 2022.
J. Wang, J. Guo y C. Li, “On The Design of a Light-weight FPGA Programming Framework for Graph Applications”, Cornell University - Computer and Science, 2022.
F. Charte, M. Espinilla, A. Rivera y F. Pulgar, “Uso de dispositivos FPGA como apoyo a la enseñanza de asignaturas de Arquitecura de Computadores”, Enseñanza y Aprendizaje de ingeniería de Computadores, nº 7, 2017.
G. Garay, A. Tchernykh, A. Yu, D. Sergey, N. Garichev, S. Nesmachnow y M. Torres, “Visualization of VHDL-based simulations as a pedagogical tool for supporting computer science education”, Journal of Computational Science, vol. 16, 2019.
R. Navas, O. Oballe, J. Castellanos y D. Rosas, “Practice Projects for an FPGA-Based Remote Laboratory to Teach and Learn Digital Electronics”, Information, vol. 14, p. 558, 2023.
Published
How to Cite
Issue
Section
License
Copyright (c) 2024 Pedro Selencio Landaeta

This work is licensed under a Creative Commons Attribution 4.0 International License.
In the event that the manuscript is approved for its next publication, the authors retain the copyright and assign to the journal the right of publication, edition, reproduction, distribution, exhibition and communication in the country of origin, as well as in the abroad, through print and electronic media in different databases. Therefore, it is established that after the publication of the articles, the authors may make other types of independent or additional agreements for the non-exclusive dissemination of the version of the article published in this journal (publication in books or institutional repositories), provided that it is explicitly indicated that the work has been published for the first time in this journal.
To record this procedure, the author must complete the following forms: